1. Field of the Invention
The present invention generally relates to an over voltage protection (OVP) apparatus and an OVP method, and more particularly, to an OVP apparatus adapted for a power supply, and an OVP method.
2. Description of Related Art
In designing a typical consumer electronic product, in order to avoid damage to the electronic product caused by prospective incorrect input of power supply, an OVP apparatus is often employed for providing further protection to the electronic product.
For example, FIG. 1 illustrates an architectural diagram of a conventional OVP circuit used for protecting a load. Referring to FIG. 1, the architecture includes an OVP apparatus 10, a conversion unit 20, a central processing unit (CPU) 30, and a power supply unit 40. The OVP apparatus 10 includes a digital-to-analog converter (DAC) 101 and a comparator 102. The conversion unit 20 includes a pulse width modulation (PWM) controller 103, a driver 104, and a buck circuit 50. The buck circuit 50 further includes an upper power transistor 105, a lower power transistor 106, an inductance 107, and a capacitor 108. The power supply unit 40 is adapted for providing a system power VCC and a standby power VSB. When the power supply unit 40 is disabled, the standby power VSB is still provided while the system power VCC stops being provided.
Typically, the operation voltage of the CPU 30 is about 1.2V to 1.4V, while the system power VCC provided by the power supply unit 40 is about 12V. Therefore, the system power VCC should be reduced to a core power VCORE (about 1.2V) by the conversion unit 20, such that the system power VCC can be provided to the CPU 30. The conversion unit is a buck converter which is well known in conventional technologies and thus is not further iterated herein. However, it should be noted that when the upper power transistor 105 suffers a sudden failure which causes a short circuit of the upper power transistor 105, the system power VCC (about 12V) would be directly outputted to the inductance 107, and sequentially to the capacitor 108 and the CPU 30. The capacitor 108 can typically endure a voltage less than or equal to 4V. Therefore, once the short circuit of the upper power transistor 105 occurs, not only the capacitor 108 is destroyed, but also the CPU 30 is damaged.
Further, in order to provide an over voltage protection, the core power VCORE is fed back to the comparator 102 of the OVP apparatus 110. The DAC 101 converts a digital signal VID provided by the CPU 30 into an analog signal. The analog signal is adjusted by an OVP trip point voltage to generate a reference voltage VREF (e.g., 2V). The reference voltage is then inputted to the comparator 102 via another input end of the comparator 102. The comparator 102 is adapted for comparing the reference voltage VREF with the core power VCORE. When the upper power transistor 105 suffers a short circuit failure and the core power VCORE becomes higher than the reference voltage VREF (i.e., 2V), the comparator 102 forces the lower power transistor 106 to be conducted via the PWM controller 103 and the driver 104. When the lower power transistor 106 is conducted, the voltage of the core power VCORE drops correspondingly, thus preventing damages caused by direct input of an over high voltage to the capacitor 108 and the CPU 30.
However, the above-discussed approach unfortunately raises an undesired serious issue. When the core power VCORE is higher than the reference voltage VREF (i.e., when the upper power transistor 105 suffers a short circuit failure), the conventional OVP apparatus 10 forces the lower power transistor 106 to be conducted. In this case, a short circuit occurs between the system power VCC and the ground GND. As such, the conducting path between the transistors 105 and 106 pulls down the voltage of the system power VCC. When the voltage of the system power VCC is lower than the operation voltage of the PWM controller 103 and the driver 104, the PWM controller 103 and the driver 104 cannot work as normal. Therefore, the lower power transistor 106 cannot remain conducted. The lower power transistor 106 thus goes back to the cutting-off status, which causes the voltage of the core power VCORE to be increased again. When the voltage of the core power VCORE becomes higher than the reference voltage VREF, the lower power transistor 106 then goes back to the conducting status, which causes the voltage of the core power VCORE to be dropped again. This process is repeated over and over, configuring an oscillation voltage. The oscillation voltage causes damages to the capacitor 108 and the CPU 30.
To resolve said issue, the conventional technology has been further proposed to provide a standby power VSB to the PWM controller 103 and the driver 104. FIG. 2 illustrates an architectural diagram of another conventional OVP circuit used for protecting a load. Referring to FIG. 2 in view of FIG. 1, the difference between the architecture of FIG. 2 and that of FIG. 1 lies in that FIG. 2 further includes additional diodes 201 to 204. When the upper power transistor 105 encounters a short circuit failure causing the core power VCORE to be higher than the reference voltage VREF (2V), the comparator 102 of the conventional OVP apparatus 10 forces the lower power transistor 106 to be conducted via the PWM 103 and the driver 104. When the lower power transistor 106 is conducted, the voltage of the core power VCORE drops correspondingly, thus preventing damages caused by direct input of an over high voltage to the capacitor 108 and the CPU 30. Forcing the lower power transistor 106 to be conducted may cause the short circuit between the system power VCC and the ground GND. As such, the conducting path configured between the transistors 105 and 106 pulls down the voltage of the system power VCC. Meanwhile, the standby power VSB provides operation power via the diodes 201 and 203 to the PWM controller 103 and the driver 104, so that the lower power transistor 106 remains conducted, thus avoiding the overly high voltage of the core power VCORE.
However, the above-discussed approach unfortunately raises another undesired serious issue. When the lower power transistor 106 remains conducted, in case the system power VCC stops supplying power, the power previously stored in the capacitor 108 is discharged to form a discharging current. The discharging current flows via the inductance 107 to the lower power transistor 106. This discharging current flowing though an equivalent series resistance (ESR) of the capacitor 108 produces a negative voltage. Generally, the CPU can tolerate a negative voltage no more than −300 mV. Unfortunately, the negative voltage produced by the discharging current often exceeds the tolerance of the CPU 30 for the negative voltage, and thus may cause damages to the CPU 30.
Accordingly, it is very much desirable for the main board manufacturers to find proper solutions to the above-discussed problems.